The invention relates to in-circuit digital testers using minimal tester memory.
In-circuit testers are capable of generating and applying digital test signals to electrical nodes of a completed logic circuit, without isolating or removing the components of the circuit from the surrounding components. Known in-circuit testers include those presented in U.S. Pat. Nos. RE 31,828 and 4,500,993, the disclosures of each of which are expressly incorporated herein by reference.
Such in-circuit testers operate by applying electrical signals, defined by a test vector which includes all tester pin states at a particular instant in time, to electrical nodes of a circuit under test. The electrical nodes are contacted by the tester pins. A vector-oriented test exercise is a table or file of such states. In printed form, vectors are typically organized as lines or rows in a file of text. Some preamble information is normally added to this file to relate elements of the vectors to pins in the tester, electrical nodes in the circuit under test, or leads of the component under test. In a file of test vectors, which together constitute a test exercise, each row of the file corresponds to the tester pin states of all participating tester pins during a particular instant in time, and each column represents the states of a single tester pin for each instant in time throughout the entire test exercise.
A file may contain thousands, even hundreds of thousands of vectors, and there may be several hundred tester pins in a tester participating. Thus, the vector file may be extremely large.
A known method of processing these vector files is to equip each tester pin with enough memory and logic to handle the corresponding column in the vector file for the entire test sequence. In operation, each tester pin is associated with a tester channel and the vector file is loaded straight into the channel memories, and then the test is run under control of a vector clock that steps the channel memories from vector to vector within the vector file. With this "RAM behind the pin" approach, memory requirements increase in direct proportion to the number of tester pins (columns) and the number of vectors (rows) in the vector file. In addition, if a channel is not active during application of a particular test vector, the channel memory is not used at all and is wasted.
One approach which has been proposed to conserve channel memory is to update the tester pin states only when the new pin state is different from the old pin state. This approach is disclosed in the above-referenced U.S. Pat No. 4,500,993 wherein the logic states of the individual tester pins are updated (toggled) under control of the vector clock only when the next logic state is different from the present logic state. Otherwise, the pin state remains unchanged. However, even though this approach reduces the amount of channel memory required for a tester (or, alternatively, allows a tester to run larger test vector files), some memory redundancy remains because the pin toggles required to change from one vector to the next within the test vector file may occur identically many times throughout the test sequence.
While this duplication is not without some advantage, in some test applications, for example, the testing of gate arrays, programmable logic devices, LSI peripheral circuits, and the like such redundancy represents inefficient use of memory.